BU4560

BU4560 On-Chip Data RAM 1 Kbyte Critical Variable Storage Single-Cycle Access 3.3 V Supply Voltage 5 V Tolerant Inputs TTL Compatible Outputs High Bandwidth Burst Bus 32-Bit Multiplexed Address/Data Programmable Memory Configuration Selectable 8-, 16-, 32-Bit Bus Widths Supports Unaligned Accesses Big or Little Endian Byte Ordering High-Speed Interrupt Controller 31 Programmable Priorities Eight Maskable Pins plus NMI Up to 240 Vectors in Expanded Mode Two On-Chip Timers Independent 32-Bit Counting Clock Prescaling by 1, 2, 4 or 8 lnternal Interrupt Sources Halt Mode for Low Power IEEE 1149.1 (JTAG) Boundary Scan Compatibility Packages 132-Lead Pin Grid Array (PGA) 132-Lead Plastic Quad Flat Pack   (PQFP) 196-Ball Mini Plastic Ball Grid Array   (MPBGA)

The BU4560 contains a permanent write protection feature that is initiated by means of a software command. After the command is transmitted, the protected area becomes irreversibly read-only despite power removal and re- application on the device. The address range of the 128 bytes of the array that is affected by this feature is 00h-7Fh. Once enabled, the permanent protection is independent of the status of the WP pin. (If WP is raised to High, the entire array is read-only. If WP is low, the region 00h-7Fh can still be read-only.)

The ADP3419 is a dual MOSFET driver optimized for driving two N-channel switching MOSFETs in nonisolated synchro- nous buck power converters used to power CPUs in portable computers. The driver impedances have been chosen to provide optimum performance in multiphase regulators at up to 25 A per phase. The high-side driver can be bootstrapped relative to the switch node of the buck converter and is designed to accommodate the high voltage slew rate associated with floating high-side gate drivers.