DF12E(3.0)-50DP-0.5V(81) DataSheet
DATASHEET
DF12E(3.0)-50DP-0.5V(81) Description
The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a pro- grammable register/latch/toggle flip-flop and the necessary clocks and control logic to allow combinatorial or registered operation. The macrocells each have two outputs, which can be fed back through the Global Routing Pool. This dual output capability from the macrocell allows efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O pad facili- tates efficient use of this feature to construct high-speed input registers.
DF12E(3.0)-50DP-0.5V(81) Features
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The DOUT_TXP and DOUT_TXN outputs are held static during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and inputs active.
DF12E(3.0)-50DP-0.5V(81) Applicatioins
Technical/Catalog InformationDF12E(3.0)-50DP-0.5V(81)VendorHirose Electric Co Ltd (VA)CategoryConnectors Connector Type