KTC8550 DataSheet
DATASHEET
KTC8550 Description
Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM´s output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off- chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.
KTC8550 Features
The KTC8550 has a differential LVPECL reference input along with an external feedback input. These features make the KTC8550 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will tristate the output buffers when driven high.
KTC8550 Applicatioins
When the internal low voltage detect circuitry senses that V2MON is low, the V2FAIL pin goes active. Typically this would be used by the processor as an interrupt to stop the execution of the code or to do housekeeping in prep- aration for an impending power failure.