MP1580HS-LF-Z DataSheet
DATASHEET
MP1580HS-LF-Z Description
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the GND terminal. 2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input. 3. The package thermal impedance is calculated in accordance with JESD 51.
MP1580HS-LF-Z Features
The MP1580HS-LF-Z is reset by holding CONFIGURE high for at least one clock cycle. Configuration occurs upon a high to low transition on the CONFIGURE pin. This transition registers COEF_DATA (6-0) into the CONFIGURATION REGISTER. Table 1 shows the meaning of each bit in the CONFIGURATION REGISTER.
MP1580HS-LF-Z Applicatioins
This IC generates a clock used for driving the CCD that configures a comb filter for Y/C separation, or for sampling A/D and D/A converters that configure a digital comb filter. It has a built-in subcarrier oscillator (3.58MHz or 4.43MHz) synchronized to the input chroma signal, and a clock oscillator that is 4 times the latter. MP1580HS-LF-ZND and NF are available for NTSC format, and MP1580HS-LF-ZPD and PF for PAL format.