STPS10H100CT DataSheet
DATASHEET
STPS10H100CT Description
The error amplifiers exhibit a common-mode voltage range from C0.3 V to VCC C2 V. The DTC comparator has a fixed offset that provides approximately 5% dead time. The on-chip oscillator can be bypassed by terminating RT to the reference output and providing a sawtooth input to CT, or it can be used to drive the common circuitry in synchronous multiple-rail power supplies.
STPS10H100CT Features
The device density is indicated using bits 5, 4, and 3 of the status register. For the STPS10H100CT, the three bits are 1, 0, and 0. The decimal value of these three binary bits does not equate to the device density; the three bits represent a combinational code relating to differing densities of Serial DataFlash devices, allowing a total of eight differ- ent density configurations.
STPS10H100CT Applicatioins
Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ 8x8 Multiply, 32-Bit Accumulate ❐ Low Power at High Speed ❐ 3.0 to 5.25 V Operating Voltage ❐ Operating Voltages Down to 1.0V Using On- Chip Switch Mode Pump (SMP) ❐ Industrial Temperature Range: -40C to +85C
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