STW9NK90Z DataSheet
DATASHEET
STW9NK90Z Description
The SAB 80C515/80C535 is a stand-alone, high-performance single-chip microcontroller based on the SAB 8051/80C51 architecture. While maintaining all the SAB 80C51 operating characteristics, the SAB 80C515/80C535 incorporates several enhancements which significantly increase design flexibility and overall system performance.
STW9NK90Z Features
Clock input for entire chip. Maximum design frequency is 66 MHz (50 percent, 5 percent duty cycle). Global logic RESET function (asynchronous). Active low pulse with minimum duration 200ns. Slave mode input signal. Starts row processing sequence of the pixel row (i.e., pixel readout, ADC conversion, and writing of data to ADC registers). The rising edge of ROW_STRT should be synchronous with the falling edge of SYSCLK. A one-clock cycle wide active high pulse. The two-wire serial interface register setting switches this pin between input and output. Slave mode input signal. An active LOW signal that enables the column counter and initiates the readout process. Causes the 10-bit output port to be updated with data on the rising edge of the system clock. The two-wire serial interface register setting switches this pin between input and output. Trigger for snapshot mode. The two-wire serial interface register setting switches this pin between input and output. No connection should be made in slave mode. Slave mode input signal. Active low pulse that resets all photodetectors, starting a new integration cycle. No connection should be made in master mode or snapshot mode. Slave mode input signal. Active low pulse that controls transfer of charge from photodetector to memory inside each pixel for the entire pixel array. No connection should be made in master mode or snapshot mode. Slave mode input signal. Active low pulse to reset all pixel memories. No connection should be made in master mode or snapshot mode. Serial port clock. Maximum frequency is 1 MHz. Bias setting voltage for VLN_AMP or VLN_OUT. VLN_AMP and VLN_OUT can be individually disconnected from their internal biases via the two-wire serial interface and driven by this input. Bias setting voltage for pixel source following operating current. Bias setting voltage for the column source follower operating current. Dark offset cancellation. Polarity of offset is set via the two-wire serial interface. Op amp bias.
STW9NK90Z Applicatioins
host processor, other STW9NK90Zs, memory or I/O transfers). Programs can be downloaded to the STW9NK90Z using DMA transfers. Asynchronous off-chip peripherals can control two DMA channels using DMA Request/Grant lines (DMAR1C2, DMAG1C2). Other DMA features include interrupt generation upon completion of DMA transfers, two-dimensional DMA, and DMA chaining for automatic linked DMA transfers.