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UPD720101GJ

UPD720101GJ

Manufacturer Part:UPD720101GJ
Part Type:Interface ICs
Manufacturer:NEC
Part ID:UPD720101GJ
Date Code:11+
Quantity Available:4183
Last Updated:2024/11/26

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Description

Features

Applications

UPD720101GJ Description

    Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.

UPD720101GJ Features

    SUMMARY DESCRIPTION The UPD720101GJ is a 8 Mbit (1Mb x8 or 512Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be per- formed using a single low voltage (5V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are writ- ten to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The

UPD720101GJ Applicatioins

    The UPD720101GJ also offers two battery-measurement inputs capable of reading battery voltages up to 6V, while operating at only 2.7V. It also has an on-chip temperature sensor capable of reading 0.3C resolution. The UPD720101GJ is available in a TSSOP-28 and a QFN-32 package.
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