VIPER12ADIP-E DataSheet
DATASHEET
VIPER12ADIP-E Description
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4 to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
VIPER12ADIP-E Features
The VIPER12ADIP-E is designed to interface directly to the PCI or PCI-X bus and operate as a 64-bit DMA bus master. This function is accomplished through a PCI bus interface unit (PBIU) containing an on-board DMA controller. The PBIU generates and samples PCI control signals, generates host memory addresses, and facilitates the transfer of data between host memory and the on-board frame buffer. It also allows the host to access the VIPER12ADIP-E internal registers and communicate with the on-board RISC processor.
VIPER12ADIP-E Applicatioins
Technical/Catalog InformationVIPER12ADIP-EVendorSTMicroelectronicsCategoryIntegrated Circuits (ICs) Packaging
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Quantity
Manufacturer
Date Code
Description
Pricing
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