XC2C256-7VQG100C DataSheet
DATASHEET
XC2C256-7VQG100C Description
The Victory66 SLC90E66 Enhanced PCI South Bridge with Ultra ATA/66MHz IDE Controller is a multi-function PCI device implementing a PCI-to-ISA bridge function, a PCI Ultra ATA/66 IDE controller function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function. As a PCI-to-ISA bridge, the SLC90E66 integrates I/O functions found in a common ISA bridge chip, that includes two DMA controllers, two interrupt controllers, an 8254 timer, and a Real Time Clock. The DMA controllers support Type-F data transfers on each of the eight channels. The SLC90E66 also supports PC/PCI and Distributed DMA protocols for PCI based DMA applications. The Interrupt Controllers support Edge or Level sensitive programmable inputs and the use of an external I/O APIC and serial interrupts. The SLC90E66 can be configured to provide chip select decoding for BIOS, RTC, keyboard controller, external microcontroller, and two programmable chip selects. The SLC90E66 can be configured as a subtractive decode bridge or as a positive decode bridge. This allows the use of a subtractive decode PCI-to-PCI bridge such as that used in a PCI/ISA docking station environment.
XC2C256-7VQG100C Features
Choose among the following memory organizations: XC2C256-7VQG100C 16,384 x 40 XC2C256-7VQG100C 32,768 x 40 XC2C256-7VQG100C 65,536 x 40 XC2C256-7VQG100C 131,072 x 40 Up to 250MHz Operation of Clocks - 4ns read/write cycle time, 3.2ns access time Users selectable input port to output port data rates, 500Mb/s Data Rate -DDR to DDR -DDR to SDR -SDR to DDR -SDR to SDR User selectable HSTL or LVTTL XC2C256-7VQG100C/Os Read Enable & Read Clock Echo outputs aid high speed operation 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable XC2C256-7VQG100Cnput/Ouput voltage 3.3V XC2C256-7VQG100Cnput tolerant Mark & Retransmit, resets read pointer to user marked position Write Chip Select (WCS) input enables/disables Write Operations Read Chip Select (RCS) synchronous to RCLK Programmable Almost-Empty and Almost-Full flags, each flag
XC2C256-7VQG100C Applicatioins
NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Per TTL-driven input (VIN = 3.4V, control inputs only). A, B, and AB pins do not contribute to ∆Icc. 3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The A, B, and AB inputs generate no significant AC or DC currents as they transition. This parameter is guaranteed but not production tested.
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Leakage Current: Capacitors shall be stabilized at