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XC2S50-5TQG144C

XC2S50-5TQG144C

Manufacturer Part:XC2S50-5TQG144C
Part Type:Programmable Logic ICs
Manufacturer:XILINX
Part ID:XC2S50-5TQG144C
Date Code:
Quantity Available:4726
Last Updated:2024/11/26

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Description

Features

Applications

XC2S50-5TQG144C Description

    The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive cycles. Then the desiralizer goes out of lock and hunts for the new data boundary (stop/start bits). In the event of loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a high-impedance state. The users system should monitor the LOCK pin in order to detect a loss of synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as previously noted.

XC2S50-5TQG144C Features

    • Other features   • Internal oscillator circuit as clock source   • INIT is prepared as a reset terminal.   • Watchdog timer reset. Software reset.   • Low power consumption modes supported: Stop mode and Sleep mode   • Gear function   • Built-in time base timer   • Package : LQFP-144, 0.5 mm pitch, 20 mm 20 mm   • CMOS technology (0.25 µm)  • Supply voltage: Dual power supplies at 3.3 V 0.3 V, 2.5 V 0.2 V

XC2S50-5TQG144C Applicatioins

    If an output channel is set to three-state condition, the TDM serial stream output will be placed in high impedance during that channel time. In addition to the per-channel three-state control, all channels on the TDM outputs can be placed in high impedance at one time by pulling the ODE input pin in LOW. This overrides the individual per- channel programming on the Connect Memory High bits.
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