XC2S100-5TQG144I DataSheet
DATASHEET
XC2S100-5TQG144I Description
Figure 1 shows a typical soldering profile for the D2 and D3 Packages when soldering a to a printed circuit board. The profile will vary from system to system and solders to solders. Factors that can affect the profile include the type of sol- dering system used, density and type of components on the board or substrate material being used. This profile shows temperature versus time. The two profiles described are based on a high density and a low density board. The type sol- der used was 62/36/2 Tin Lead Silver with a melting point between 177-189ºC. An convection/infrared soldering reflow system was used. The circuit and solder joints heat up first due to their mass followed by the components which typi- cally run 30 degrees cooler than the solder joints.
XC2S100-5TQG144I Features
Serial Clock (SCK) - This pin is used to synchronize the communication between the microcontroller and the IS25C64, IS25C32. Op-codes, byte addresses, or data present on the SI pin and latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK for SPI modes (0,0 & 1,1).
XC2S100-5TQG144I Applicatioins
Extended data out does not place the data in / data out pins (DQs) into the high-impedance state with the rising edge of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM decodes the next address. OE and W can control the output impedance. Descriptions of OE and W further explain EDO operation benefit.
Relate Parts
Part Number
Quantity
Manufacturer
Date Code
Description
Pricing
10241
11+
PARAMETER Reference Voltage Section Fb Voltage
13752
11+
The floating-point register file is made u
13848
Hardware Reset, active Low. Provides a hardware me
5208
A high on the MASTER RESET (MR) sets all the cont
14048
Addresses and chip enables are registered at risin
16717
The XC5200 Field-Programmable Gate Array Family i
15491
Wiper position programming defaults to midscale a
17695
The CS5381 uses a 5th-order, multi-bit delta-sigma
8886
The mounting area was reduced by mak- ing the tw
13759
The A-to-B enable (CEAB) input must be low in ord
17911
via an RF or an infrared transmission medium upo
4950
Note 2: The maximum power dissipation is dictated
4838
The BRT (Bias Resistor Transistor) contains
4726
The deserializer stays in lock until it cannot de
8877
Output, Pin 14, is suitable for controlling a pow
3499
The challenge for an integrated clock-recovery cir
14663
Programmable low and high gain (<2 dB resoluti
19152
For example, if a block of data is to be transfer
15000
IC ground Enable/disable Control input (duty cyc
7530
These data selectors/multiplexers contain invert