XC95288XL-10PQG208C DataSheet
DATASHEET
XC95288XL-10PQG208C Description
The challenge for an integrated clock-recovery circuit is to meet the jitter specification recommended by the International Telecommunication Union-Telecom Standards Sector (ITU- T). Jitter refers to the effect in which individual bit transitions ("0" to "1" and vice-versa) are not exactly in phase. The effect becomes visual in an "eye diagram," in which several pseudo- random bit-pattern sequences are superimposed. An eye diagram illustrates the quality of a data stream in terms of the eye opening, measured using the "eye mask" (Figure 2).
XC95288XL-10PQG208C Features
Timing Diagrams Power-up Sequence Default Wake-up Selection Control Bus Timing Diagram Output Enable by Pin OE Timing of the Test Access Port TAP Timing of all Pins connected to the Boundary-Scan-Register-Chain Timing Diagram of the Digital Video Interface Characteristics, Clock Signals
XC95288XL-10PQG208C Applicatioins
The XC95288XL-10PQG208C also features a low-power shutdown mode for extended battery life. A reference bypass pin has been provided to improve PSRR perform- ance and output noise, by connecting a small external capacitor from the XC95288XL-10PQG208C´s reference output to ground.
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Note 2: The maximum power dissipation is dictated