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XC2S400E-6FTG256C

XC2S400E-6FTG256C

Manufacturer Part:XC2S400E-6FTG256C
Part Type:Programmable Logic ICs
Manufacturer:XILINX
Part ID:XC2S400E-6FTG256C
Date Code:
Quantity Available:16545
Last Updated:2024/11/26

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Description

Features

Applications

XC2S400E-6FTG256C Description

    Output Bit Driver Voltage Supply Ground Output Enable: HI = High Impedance; LO or Floating: Normal Operation Power Down: HI = Power Down; LO = Normal HI = Binary Twos Complement; LO = Straight Binary Ground Reference Select 2: See Table on Page 5. Reference Select 1: See Table on Page 5. Internal Reference Voltage Ground Ground Ground Ground Bottom Reference Voltage Bypass Common-Mode Voltage (mid-scale) Top Reference Voltage Bypass Ground Ground Complementary Analog Input Ground Analog Input Supply Voltage Supply Voltage

XC2S400E-6FTG256C Features

    • Integrated 600V half-bridge gate driver • 15.6V zener clamp on Vcc • True micropower start up • Tighter initial deadtime control • Low temperature coefficient deadtime • Shutdown feature (1/6th Vcc) on CT pin • Increased undervoltage lockout Hysteresis (1V) • Lower power level-shifting circuit • Constant LO, HO pulse widths at startup • Lower di/dt gate driver for better noise immunity • Low side output in phase with RT • Internal 50nsec (typ.) bootstrap diode (XC2S400E-6FTG256CD) • Excellent latch immunity on all inputs and outputs • ESD protection on all leads • Also available LEAD_FREE

XC2S400E-6FTG256C Applicatioins

    The receive cell data to the ATM layer from the receive FIFO. This is updated on the rising edge of RFCLK. RDAT[7:0] is tristated if TSEN is asserted or if MPHYEN is asserted. In UTOPIA single-phy mode, it is driven if RRDENB is asserted (TSEN also asserted) or always driven if TSEN is low. In UTOPIA multi-phy mode, RDAT[7:0] is driven following the level-2 protocol. Pin #: RDAT0/70, RDAT1/71, RDAT2/74, RDAT3/75, RDAT4/76, RDAT5/77, RDAT6/78, RDAT7/79
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