XC95288XL-10TQG144I DataSheet
DATASHEET
XC95288XL-10TQG144I Description
Drive Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 22 ns 6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible Eight D-Type Flip-Flops in a Single Package Full Parallel Access for Loading
XC95288XL-10TQG144I Features
The upper and lower gates are held low until the driver is initialized. Once the VCC voltage surpasses the VCC Rising Threshold (See Electrical Specifications), the PWM signal takes control of gate transitions. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [TPDLLGATE], the lower gate begins to fall. Typical fall times [TFLGATE] are provided in the Electrical Specifications section. Adaptive shoot-through circuitry monitors the LGATE voltage and determines the upper gate delay time [TPDHUGATE] based on how quickly the LGATE voltage drops below 1.0V. This prevents both the lower and upper MOSFETs from conducting simultaneously or shoot-through. Once this delay period is complete the upper gate drive begins to rise [TRUGATE] and the upper MOSFET turns on.
XC95288XL-10TQG144I Applicatioins
(a) A1 selection A2 selection A3 selection A4 selection A5 selection A6 selection A7 selection A8 selection A9 selection A10 selection A11 selection A12 selection I/O expander (serialparallel conversion) I/O expander (parallelserial conversion) I/O expander status setup
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