XC3S400-4TQG144C DataSheet
DATASHEET
XC3S400-4TQG144C Description
26-42 MIPS Integer Performance 3.5-5.6 MFLOPS Floating-Point-Performance IEEE 754-Compatible FPU Independent Instruction and Data MMUs 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed Simultaneously 32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface User-Object-Code Compatibility with All Earlier TS68000 Microprocessors Multimaster/Multiprocessor Support via Bus Snooping Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize Throughput 4G bytes Direct Addressing Range Software Support Including Optimizing C Compiler and UNIX® System V Port IEEE P 1149-1 Test Mode (JTAG) f = 25 MHz, 33 MHz; VCC = 5V 5%; PD = 7W The Use of the TS88915T Clock Driver is Suggested
XC3S400-4TQG144C Features
• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection - Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology - Endurance: 100K Program/Erase Cycles - Data Retention : 10 Years • Command Register Operation • Intelligent Copy-Back • Unique ID for Copyright Protection • Package - XC3S400-4TQG144CXXU0A-YCB0/YIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - XC3S400-4TQG144C-VCB0/VIB0 48 - Pin WSOP I (12X17X0.7mm) - XC3S400-4TQG144CXXU0A-PCB0/PIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package - XC3S400-4TQG144C-FCB0/FIB0 48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package * XC3S400-4TQG144C-V,F(WSOPI ) is the same device as XC3S400-4TQG144C-Y,P(TSOP1) except package type.
XC3S400-4TQG144C Applicatioins
27 MHz master clock (internal PLL reference clock) Generated clocks • 27 MHz output • 33.8688 MHz output • 384fs output • 512fs output • 768fs output Sampling frequency fs • 44.1/48 kHz Output disable function Low jitter output: 100 ps (typ, 15pF load) Supply voltage: 3.3 V 24-pin VSOP package
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Date Code
Description
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